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{{T}}
[[Category:English]]
[[Category:Digital Electronics]]
{{BR}}
= Introduction =
'''Digital electronics''' studies circuits that represent, process, store, and transmit information using a finite set of signal levels, most commonly two levels interpreted as binary 0 and 1. At university level, the subject connects [[English:Boolean algebra|Boolean algebra]], [[English:Logic gate|logic gates]], transistor-level implementation, timing, state, and systematic digital design. You should learn to move between an abstract logical specification and a physical circuit whose voltage, delay, loading, and synchronization constraints matter.

[[File:Analog digital signal.svg|500px|frameless|center]]

{{#ev:youtube|https://www.youtube.com/watch?v=DBTna2ydmC0|500|center}}

A digital value is not a perfectly mathematical 0 or 1 inside real hardware. It is represented by a voltage or another physical quantity that lies inside ranges defined by a logic family. Signals require finite time to change, wires and gates add capacitance, and noise can disturb a value. For this reason, reliable digital design combines discrete logic with analog awareness.

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== Learning Goals ==
After completing this aiMOOC, you should be able to explain binary logic levels, construct and simplify Boolean functions, design combinational and sequential circuits, interpret timing constraints, compare common storage and selection structures, model finite-state machines, and reason about the physical implementation of digital logic. You should also be able to test a design systematically and communicate it through truth tables, state diagrams, timing diagrams, schematics, or a [[English:Hardware description language|hardware description language]].

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= Digital Representation and Logic Levels =
A binary digital system uses two symbolic states. The symbols 0 and 1 are convenient abstractions, while actual gates recognize input-voltage ranges and produce output-voltage ranges. A robust logic family leaves a region between guaranteed low and high levels so that modest disturbances do not immediately change the interpreted state. This tolerance is described by '''noise margin'''.

[[File:Digital Signal Square Wave.svg|500px|frameless|center]]

Real transitions have rise time and fall time rather than changing instantaneously. A signal can therefore spend a short interval between valid low and high regions. Digital designers must also account for fan-out, capacitive loading, electromagnetic interference, supply variation, and temperature. These nonideal effects become especially important at high clock rates or across long interconnections.

Binary numbers provide the numerical layer above logic levels. An unsigned n-bit word represents values from 0 through 2^n - 1. Signed integers are commonly represented in [[English:Two's complement|two's complement]], which makes addition and subtraction convenient in hardware. Hexadecimal notation is widely used because each hexadecimal digit corresponds exactly to four binary bits.

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== Logic Families and CMOS ==
Modern integrated digital circuits are commonly implemented using [[English:CMOS|CMOS]] technology. A CMOS inverter uses a complementary PMOS and NMOS transistor network so that one device network pulls the output high while the other pulls it low under steady-state logic conditions.

[[File:CMOS inverter.svg|500px|frameless|center]]

Dynamic CMOS power is strongly associated with charging and discharging capacitances during transitions. A useful first-order model is P ≈ α C_L V_DD² f, where α is an activity factor, C_L is effective load capacitance, V_DD is the supply voltage, and f is switching frequency. Real chips also dissipate leakage power and short-circuit power during transitions.

Integrated logic has evolved through several logic families and integration scales. The 7400 series is historically important because it made standardized logic functions available as integrated circuits and remains useful for teaching gate-level design.

[[File:RIFA 7400 Integrated Circuit.jpg|500px|frameless|center]]

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= Boolean Algebra and Logic Gates =
[[English:Boolean algebra|Boolean algebra]] expresses logical relationships using variables that take two values. The basic operations are NOT, AND, and OR. Derived gates such as NAND, NOR, XOR, and XNOR are convenient because they directly express frequently used functions. NAND and NOR are '''functionally complete''': either gate type alone can be combined to implement any Boolean function.

[[File:Logic Gates.svg|500px|frameless|center]]

{{#ev:youtube|https://www.youtube.com/watch?v=WW-NPtIzHwk|500|center}}

For variables A and B, AND is 1 only when both inputs are 1, OR is 1 when at least one input is 1, and XOR is 1 when exactly one of two inputs is 1. A NOT gate complements its input. Truth tables provide an exhaustive description of a Boolean function when the number of variables is manageable.

{| class="wikitable" align="center"
! A
! B
! A AND B
! A OR B
! A XOR B
|-
| 0
| 0
| 0
| 0
| 0
|-
| 0
| 1
| 0
| 1
| 1
|-
| 1
| 0
| 0
| 1
| 1
|-
| 1
| 1
| 1
| 1
| 0
|}

Two of [[English:De Morgan's laws|De Morgan's laws]] are NOT(A AND B) = NOT A OR NOT B and NOT(A OR B) = NOT A AND NOT B. These identities are central when transforming circuits into NAND-only or NOR-only forms and when moving inversion through a logic network.

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== Canonical Forms ==
A Boolean function can be written as a '''sum of products''' or a '''product of sums'''. Canonical forms use minterms or maxterms that include every variable. They are systematic but not always economical, so designers simplify expressions before implementation when area, delay, or power matters.

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= Combinational Logic =
A '''combinational circuit''' has outputs determined by the current input values, ignoring propagation delay. There is no stored state in the logical model. Important building blocks include adders, subtractors, comparators, decoders, encoders, multiplexers, shifters, and arithmetic logic units.

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== Adders ==
A half adder adds two one-bit inputs and produces a sum and carry. A full adder adds A, B, and a carry-in. Its sum is A XOR B XOR C_in, while its carry-out is 1 when at least two of the three inputs are 1. Chaining full adders forms a ripple-carry adder, but the carry path can become the critical delay for large word widths.

[[File:Full-adder logic diagram.svg|500px|frameless|center]]

Faster arithmetic structures reduce carry-propagation delay by computing carry information more aggressively. Examples include carry-lookahead, carry-select, and parallel-prefix adders. Their value illustrates a recurring digital-design trade-off: extra hardware can reduce latency.

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== Multiplexers and Decoders ==
A [[English:Multiplexer|multiplexer]] selects one of several data inputs according to select inputs. A 4-to-1 multiplexer uses two select bits to choose one of four inputs. Multiplexers can implement arbitrary Boolean functions and are also essential for routing data between registers and functional units.

[[File:Multiplexer 4-to-1.svg|500px|frameless|center]]

A decoder activates one output corresponding to a binary input code, while an encoder performs a related reverse mapping. Priority encoders resolve cases in which multiple input requests are active. When you choose among these structures, pay attention to active-high versus active-low conventions and whether enable inputs are present.

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= Logic Simplification =
Simplification seeks an equivalent Boolean function with lower implementation cost. Algebraic manipulation, [[English:Karnaugh map|Karnaugh maps]], and algorithmic minimization methods can reduce the number of terms or literals. A Karnaugh map arranges truth-table cells in Gray-code order so adjacent cells differ in only one variable. Grouping adjacent 1-cells in powers of two leads to simplified sum-of-products expressions.

[[File:Karnaugh map KV 4mal4 Gruppe05.svg|500px|frameless|center]]

{{#ev:youtube|https://www.youtube.com/watch?v=J_t_7npo0CE|500|center}}

A minimal expression is not always the best physical implementation. Designers may deliberately add redundant logic to avoid hazards, share common subexpressions, or choose a structure that maps efficiently to a target [[English:Field-programmable gate array|field-programmable gate array]] or standard-cell library.

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== Hazards ==
A '''hazard''' is an unwanted temporary output change caused by unequal propagation delays along different paths. Static and dynamic hazards can appear even when the Boolean expression is correct in steady state. Hazard analysis matters in asynchronous control signals and other circuits in which a brief pulse can trigger unwanted behavior.

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= Sequential Logic =
A '''sequential circuit''' combines logic with stored state. Its output may depend on current inputs and on the history represented by that state. Latches and flip-flops are fundamental storage elements. Registers combine multiple storage elements to hold words, while counters update state according to a defined sequence.

[[File:JK Flip-flop.svg|500px|frameless|center]]

{{#ev:youtube|https://www.youtube.com/watch?v=HZg7fNu-l24|500|center}}

A latch is level-sensitive, while an edge-triggered flip-flop samples data around a clock edge. A D flip-flop is widely used because its next state is directly determined by D at the active edge, subject to timing requirements. JK and T flip-flops are useful for understanding toggling behavior and counter construction.

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== Registers and Counters ==
A register is a group of flip-flops that stores a multi-bit value. Registers may support parallel load, shifting, reset, enable, or other control functions. Shift registers move data by one or more positions per clock and can support serial-to-parallel or parallel-to-serial conversion.

A counter is a sequential circuit that advances through a state sequence. In an asynchronous ripple counter, one stage can clock the next, causing cumulative delay. In a synchronous counter, state bits share a common clock and next-state logic determines which bits change.

[[File:4-bit-jk-flip-flop.svg|500px|frameless|center]]

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= Finite-State Machines =
A [[English:Finite-state machine|finite-state machine]] models behavior as a finite set of states and transitions. In a Moore machine, outputs depend on the current state. In a Mealy machine, outputs can depend on the current state and current inputs. Both models can implement the same broad classes of sequential behavior, but they may differ in state count, output timing, and sensitivity to input changes.

[[File:Finite-State-Machine.svg|500px|frameless|center]]

A systematic synchronous FSM workflow is to define states, define inputs and outputs, create a state-transition representation, choose a state encoding, derive next-state and output logic, implement the state register, and verify reachable as well as exceptional conditions. Reset behavior must be specified deliberately rather than treated as an afterthought.

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= Timing, Synchronization, and Reliability =
Functional correctness is not enough. Every physical gate and wire has delay. The '''propagation delay''' of a path is the time between an input transition and the corresponding stable output response. In synchronous systems, the longest relevant combinational path between registers helps determine the minimum safe clock period.

[[File:Logic signal waveform.svg|500px|frameless|center]]

A receiving flip-flop requires its input to be stable for a '''setup time''' before the active clock edge and a '''hold time''' after that edge. Violating these requirements can drive the device into '''metastability''', a temporary state in which its output does not promptly resolve to a valid logic level. Metastability cannot be eliminated from asynchronous sampling in an absolute sense, but its probability of causing a system failure can be reduced with synchronizers, suitable timing margins, and correct clock-domain-crossing design.

Clock skew and clock jitter change the effective timing available between sequential elements. Designers therefore analyze maximum-delay paths for setup constraints and minimum-delay paths for hold constraints. Timing closure is the process of ensuring that required paths meet their constraints under the intended operating conditions.

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== Clock-Domain Crossing ==
When a signal crosses between unrelated clock domains, simply connecting one register domain to another can produce unreliable behavior. A common technique for a single slowly changing control bit is a multi-stage synchronizer. Multi-bit data usually needs a protocol such as a handshake, toggle scheme, Gray-coded pointer, or asynchronous FIFO so that related bits remain coherent.

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= Hardware Description and Verification =
Large digital systems are rarely designed by drawing every gate. A [[English:Hardware description language|hardware description language]] such as VHDL or Verilog describes combinational and sequential behavior, hierarchy, and interfaces. Synthesis tools transform synthesizable descriptions into a network of hardware resources for an FPGA or ASIC implementation.

A testbench supplies stimuli and checks responses in simulation. Good verification includes normal cases, boundary cases, illegal or unexpected inputs, reset behavior, and temporal sequences. Assertions can state properties such as protocol rules or invariants. For complex designs, verification effort can exceed the effort required to write the hardware description itself.

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== A Practical Design Method ==
# [[English:Specification|Specification]]: State what the circuit must do, define interfaces, clocking, reset behavior, and measurable constraints.
# [[English:Boolean function|Boolean function]]: Express combinational requirements with truth tables, equations, or behavioral logic.
# [[English:Finite-state machine|Finite-state machine]]: Model required history explicitly when outputs depend on previous events.
# [[English:Simulation|Simulation]]: Check functional behavior before implementation and include edge cases.
# [[English:Timing analysis|Timing analysis]]: Verify that the physical implementation satisfies setup, hold, clock, and interface constraints.
# [[English:Hardware testing|Hardware testing]]: Compare measured behavior with the specification and investigate discrepancies systematically.

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= Interactive Tasks =
{{BR}}
== Quiz: Test Your Knowledge ==
{{MC}}

'''What defines a combinational circuit at the logical level?'''
(Its outputs depend only on the present input values)
(!Its outputs depend only on previous clock edges)
(!It must contain at least one flip-flop)
(!It can operate only with analog voltages)

{{E}}
<br>

{{MC}}

'''For a two-input XOR gate, when is the output equal to 1?'''
(When the two input values are different)
(!When both input values are 0)
(!When both input values are 1)
(!When at least one input value is 0)

{{E}}
<br>

{{MC}}

'''Which statement is a form of De Morgan's law?'''
(The complement of A AND B equals NOT A OR NOT B)
(!The complement of A AND B equals A OR B)
(!The complement of A OR B equals A AND B)
(!The complement of A equals A)

{{E}}
<br>

{{MC}}

'''What does a one-bit full adder produce?'''
(A sum bit and a carry-out bit)
(!Only a sum bit)
(!Only a carry-in bit)
(!A clock signal and a reset signal)

{{E}}
<br>

{{MC}}

'''What is the main function of a multiplexer?'''
(To select one of several data inputs)
(!To store one bit indefinitely without power)
(!To convert every input into an analog voltage)
(!To generate a clock from a crystal)

{{E}}
<br>

{{MC}}

'''What does an edge-triggered D flip-flop primarily store?'''
(The value of D sampled around the active clock edge)
(!The sum of all inputs since power-up)
(!A continuously varying analog amplitude)
(!The clock frequency as a decimal number)

{{E}}
<br>

{{MC}}

'''Why must setup and hold requirements be respected?'''
(To allow a flip-flop to capture data reliably)
(!To guarantee that all gates consume zero power)
(!To remove the need for a clock network)
(!To make every combinational path have equal delay)

{{E}}
<br>

{{MC}}

'''What is metastability in a digital storage element?'''
(A temporary unresolved state after a critical timing event)
(!A permanently valid third logic level used for arithmetic)
(!A method for reducing Boolean expressions)
(!A type of combinational decoder)

{{E}}
<br>

{{MC}}

'''What primarily contributes to dynamic switching power in CMOS logic?'''
(Charging and discharging capacitances during transitions)
(!Storing binary numbers in truth tables)
(!Using only odd binary values)
(!Keeping every transistor permanently off)

{{E}}
<br>

{{MC}}

'''In a synchronous finite-state machine, where is the current state normally held?'''
(In a register updated by a clock)
(!In a purely passive resistor network)
(!In the truth table of an external textbook)
(!In an unclocked analog integrator)

{{E}}
<br>

{{BR}}
== Memory Game ==
<div class="memo-quiz">
{|
|-
| Noise margin || Tolerance between guaranteed logic levels and decision thresholds
|-
| Multiplexer || Circuit that selects one data input from several alternatives
|-
| Full adder || Circuit that adds two bits together with a carry-in
|-
| Register || Group of storage elements that holds a multi-bit word
|-
| Metastability || Temporary unresolved behavior after critical sampling timing is violated
|-
| Karnaugh map || Gray-code arrangement used to simplify Boolean functions
|}
{{E}}
<br>

{{BR}}
== Drag and Drop ==
<div class="lueckentext-quiz">

{| class="wikitable"
! Match the correct terms.
! Topic
|-
| '''Combinational logic'''
| Output depends on current inputs
|-
| '''Sequential logic'''
| Output can depend on stored state
|-
| '''Decoder'''
| Activates an output associated with an input code
|-
| '''Synchronizer'''
| Reduces risk when sampling an asynchronous control signal
|-
| '''Critical path'''
| Longest relevant delay path limiting clock speed
|}
{{E}}

<br>
...
<br />

{{BR}}
== Crossword Puzzle ==
<div class="kreuzwort-quiz">
{|
|-
| Binary || Which numeral system uses only zero and one?
|-
| Boolean || Which algebra models variables with two truth values?
|-
| Inverter || Which gate outputs the complement of its input?
|-
| Multiplexer || Which circuit selects one of several data inputs?
|-
| Register || Which structure stores a multi-bit word using storage elements?
|-
| Metastability || What temporary uncertain state can follow a setup or hold violation?
|}
{{E}}
<br>

{{BR}}
== LearningApps ==
<iframe> https://learningapps.org/index.php?s=Digital+Electronics </iframe>

{{BR}}
== Cloze Text ==
<quiz display=simple>
{'''Complete the text.'''<br>
|type="{}"}
Digital circuits usually represent information with { discrete } signal levels. Boolean functions can be described exhaustively with a { truth table }. A NAND gate is useful because it is { functionally complete }. A multiplexer uses select inputs to choose one { data } input. A full adder includes a carry input and produces a { carry-out } bit. A flip-flop provides a basic element for storing { state }. Synchronous circuits coordinate state changes with a { clock }. A Karnaugh map uses Gray-code adjacency to support logic { simplification }. Setup and hold constraints protect reliable { sampling }. A timing violation can cause temporary { metastability }. CMOS dynamic power rises with switching activity and effective load { capacitance }. Hardware descriptions should be checked with systematic { verification }.
</quiz>

<br>

{{BR}}
= Open-Ended Tasks =
{{BR}}
=== Easy ===
# [[English:Truth table exercise|Truth table exercise]]: Choose three two-input logic gates, create complete truth tables, and explain in your own words how each output depends on its inputs.
# [[English:Binary conversion|Binary conversion]]: Create a one-page study sheet that converts several unsigned binary values to decimal and hexadecimal and explains why hexadecimal is convenient for digital systems.
# [[English:Logic gate poster|Logic gate poster]]: Produce a clear image or diagram showing NOT, AND, OR, NAND, NOR, XOR, and XNOR symbols with one practical interpretation for each.
# [[English:Circuit observation|Circuit observation]]: Use a simulator or laboratory trainer to test a simple gate circuit, record input and output values, and compare your measurements with the expected truth table.

{{BR}}
=== Standard ===
# [[English:Combinational circuit design|Combinational circuit design]]: Design a three-input majority detector, derive its Boolean expression, simplify it, draw a gate-level circuit, and test every input combination.
# [[English:Adder investigation|Adder investigation]]: Build or simulate a full adder, measure or estimate its propagation delay, and explain how delay accumulates in a ripple-carry adder.
# [[English:Multiplexer project|Multiplexer project]]: Implement a Boolean function using a multiplexer, document the select mapping, and compare the result with a direct gate-level implementation.
# [[English:Sequential circuit video|Sequential circuit video]]: Create a short explanatory video that demonstrates how a D flip-flop and a small register respond to clock edges, reset, and changing data.

{{BR}}
=== Advanced ===
# [[English:Finite-state machine project|Finite-state machine project]]: Design a synchronous controller for a realistic process, create its state diagram and transition table, implement it in an HDL or simulator, and test normal and exceptional sequences.
# [[English:Clock-domain crossing investigation|Clock-domain crossing investigation]]: Research a two-stage synchronizer and an asynchronous FIFO, model the problem each solves, and explain why a simple direct connection can be unsafe.
# [[English:Timing experiment|Timing experiment]]: Construct a simulation or laboratory experiment that varies combinational delay relative to a clock, then identify setup or hold failures and document the observed consequences.
# [[English:Digital design interview|Digital design interview]]: Interview an engineer, laboratory technician, or researcher about digital verification, FPGA or ASIC workflows, and timing closure, then compare the professional process with the design method used in this course.

{{:Open Task - Create a MOOC}}

{{BR}}
= Learning Assessment =
# [[English:Boolean reasoning assessment|Boolean reasoning assessment]]: Given a logic specification, derive a Boolean function, transform it using De Morgan's laws, and justify whether the transformed circuit is equivalent under all input combinations.
# [[English:Combinational architecture assessment|Combinational architecture assessment]]: Compare two implementations of the same arithmetic function and argue which is preferable under different area, delay, and power constraints.
# [[English:Sequential design assessment|Sequential design assessment]]: Convert a behavioral requirement into a finite-state machine, select a state encoding, derive next-state logic, and explain how reset behavior affects the design.
# [[English:Timing analysis assessment|Timing analysis assessment]]: Analyze a register-to-register path with stated clock period, propagation delay, setup time, hold time, skew, and uncertainty, then determine whether the design has adequate timing margin.
# [[English:Synchronization assessment|Synchronization assessment]]: Evaluate an asynchronous input crossing into a synchronous system, propose a suitable synchronization strategy, and explain what risk remains even after mitigation.
# [[English:Verification assessment|Verification assessment]]: Develop a compact verification plan for a digital module, including boundary cases, temporal sequences, assertions or invariants, and criteria for deciding that testing is sufficient.

<br>
<br>

{{BR}}
= Evidence of Learning =
; Knowledge
: You can explain logic levels, Boolean operations, combinational and sequential structures, state machines, CMOS switching, propagation delay, setup and hold constraints, and metastability.
; Skills
: You can derive truth tables and Boolean equations, simplify logic, design datapath and control structures, interpret timing diagrams, analyze critical paths, and verify circuit behavior with simulation or laboratory measurements.
; Products
: Strong evidence includes correct schematics, state diagrams, timing analyses, HDL modules, testbenches, laboratory records, design reports, and explanatory media that make assumptions and results traceable.
; Transfer achievements
: You can apply the same reasoning to unfamiliar digital systems, compare implementation trade-offs, diagnose discrepancies between ideal logic and physical behavior, and choose appropriate synchronization and verification methods for new interfaces.

<br>
<br>

{{BR}}
= OERs on the Topic =
The embedded English Wikipedia article provides an openly accessible overview that you can use for orientation and further reading. For device-specific voltage, timing, and loading limits, use the current datasheet for the actual component or technology you are designing with.

<iframe> https://en.m.wikipedia.org/wiki/Digital_electronics </iframe>

<br>

{{BR}}
= Linked Learning Areas =
{| align=center
{{:D-Tab}}
'''[[English:Digital Electronics|Digital Electronics]]'''
# [[English:Binary number|Binary number]]
# [[English:Boolean algebra|Boolean algebra]]
# [[English:Logic gate|Logic gate]]
# [[English:Combinational logic|Combinational logic]]
# [[English:Sequential logic|Sequential logic]]
# [[English:Flip-flop|Flip-flop]]
# [[English:Register|Register]]
# [[English:Finite-state machine|Finite-state machine]]
# [[English:CMOS|CMOS]]
# [[English:Hardware description language|Hardware description language]]
|}

{{BR}}
= aiMOOC Projects =
[[Category:English]]
[[Category:Digital Electronics]]
[[Category:Higher Education]]
[[Category:Electrical Engineering]]
[[Category:Computer Engineering]]
[[Category:Digital Logic]]
[[Category:Electronics]]
[[Category:Computer Science]]
[[Category:AI_MOOC]]
[[Category:GPT aiMOOC]]
{{MT}}

English:Digital Electronics - Versionsgeschichte

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